A3959.Frequently Asked Questions

提供以下保护功能:
热关闭(TSD)
Undervoltage lockout (UVLO)
交叉电流保护
VREG and charge pump monitors
A3959的正确操作需要以下组件:
  • PWM电流控制电路需要RS,外部检测电阻。这应该是一个非顽固式电阻类型。建议的最大RS值可以使用RS = 0.5 / ITRIP(MAX)来计算。使用合理较小的RS值将在RS中耗散较少的功率并提供净空。还需要与检测电阻平行有0.1μF单声道/陶瓷电容器。
  • 必须在CP1和CP2引脚之间放置0.22μF单声道/陶瓷电容器。
  • The VREG pin should be decoupled with a 0.22 µF capacitor to ground.
  • 建议使用逻辑电源(VDD)去耦电容:陶瓷,额定为0.1μF。
  • 建议使用负载电源(VBB)去耦电容:电解,额定值>47μF。此外,如果高频问题是一个问题,应平行放置0.1μF陶瓷电容。
  • If the SLEEP pin is not used, a 1 kΩ pull-up resistor to VDD is required
Not necessarily. The inputs can be tied directly to VDD or ground, depending on the logic level you desire. If pull-up/pull-down resistors are required for your particular design, 1 k to 4.7 kΩ resistors are recommended.
50 V.这不得在任何情况下超出。
The output current rating is for continuous current. The A3959 can handle a peak current of 6 A for <3 µs. Note: When running at high currents, power dissipation should be carefully considered. Caution should be taken to never exceed a junction temperature of 150°C when running the device.
The A3959 provides constant-current control. Motor winding current is controlled by an internal PWM current-control circuit, which incorporates an internal OSC circuit to set the fixed off-time, which is typically 24 µs.
Yes. The sense resistor, RS, should be connected as close as possible to the device. The ground side of RS should return on a separate trace to the ground pin(s) of the device. RS should be noninductive, and the circuit board traces should be as large as physically possible. A 47 µF or larger electrolytic decoupling capacitor should be placed between the load supply pins and ground, and be placed as close as physically possible to the device.
一个地面面积,至少比包装大纲大的两倍是一个很好的开始。有关进一步的布局考虑,请参阅Allegro网站上的以下内容:“Package Thermal Characteristics".
Use of external Schottky diodes with low VFORWARD, to clamp the outputs to VBB and ground, will help to reduce the power dissipation in the A3959. Heat sinks are also a possibility, but not as efficient.
There is no application note about using external diodes on the A3959. Each of the outputs should have one Schottky diode connected to VBB (cathode to VBB) and one Schottky diode connected to ground (anode to ground, not to the sense pins). If the PFD1 and PDF2 input pins are set to "slow decay only," then use only two Schottky diodes between the outputs and ground. The two Schottky diodes from the outputs to VBB will not help improve thermal performance in slow decay mode.
由于可以使用的电压和电流范围,我们通常不推荐特定二极管。
It is possible. However, there are several considerations, such as optimization of circuit board layout, use of heat sinks, etc. Please refer to application note numbers: AN29501.4,"Computing IC Temperature Rise“和29501.5,"Improving Batwing Power Dissipation".
Absolutely. The A3959 has Sleep mode, which minimizes power consumption when not in use. During Sleep mode, the device draws a maximum of 20 µA.
Unfortunately, not at this time. However, the datasheet and these FAQs address the majority of the questions regarding the A3959.
不可以。由于其3个能力,A3959通常是比大多数典型电机驱动器IC更具成本效益的解决方案。